Intel Xeon E5310
Runs in an LGA 775 board only with the adapter sticker, the socket tabs removed and BIOS support for its core. How the mod works.
Intel Xeon E5310: 4-core, 1.6 GHz, Clovertown, LGA 771, 1066 MT/s FSB, 8 MB (2 x 4 MB) L2, 80 W TDP.
Four 65 nm Clovertown cores at 1.6 GHz make the E5310 the slowest of the 80 W E-series quads in this database. It runs a 1066 MT/s bus and a 6x multiplier, and the package holds two dual-core dies with 4 MB of L2 each. On SpeedStep the sources split: ARK says it has Enhanced SpeedStep, but Intel's spec update lists no EIST for SL9XR, SLACB or SLAEM, so the table says no, and the chip lacks Intel's clock and voltage scaling. VT-x is there, SSE4.1 is not. It makes sense as a file server or a small host for a few virtual machines, where four cores count for more than clock speed.
| Family | Xeon |
|---|---|
| Codename | Clovertown |
| Socket | LGA 771 |
| Cores / threads | 4 / 4 |
| Base clock | 1.6 GHz |
| Front-side bus | 1066 MT/s (267 MHz base clock) |
| Multiplier | 6x |
| L2 cache | 8 MB (2 x 4 MB) |
| TDP | 80 W |
| Process | 65 nm |
| Launch | Q4 2006 |
| Dual-socket capable | Yes |
| VT-x | Yes |
| SSE4.1 | No |
| Enhanced SpeedStep | No |
| Max case temperature | 66 °C |
| Voltage range (VID) | 1 V to 1.5 V |
Steppings and microcode IDs
| Stepping | CPUID | sSpec |
|---|---|---|
| B3 | 6F7 | SL9XR, SLACB |
| G0 | 6FB | SLAEM |
A BIOS needs a microcode update matching the CPUID (and, for Xeons, the LGA 771 platform ID). See LGA 771 Xeon microcode and how to read your stepping.
Mod notes
Stick the adapter on the chip, cut the two key tabs from the LGA 775 socket, and add microcode for CPUIDs 6F7 and 6FB with the LGA 771 platform ID to a board that already runs Kentsfield quad cores. Removing the tabs is permanent, and the blade works a hair away from pins that bend at a touch.
Check a specific board with the LGA 771 to 775 compatibility checker.